Sixty Second Timer
Objective- The goal of this project was to create a timer that counted up to 59 seconds and then reset at zero. The tens place circuit had to be created with SSI asynchronous counters, specifically J/K flip flops, and the ones place was to be implemented with an MSI synchronous counter, namely a 74LS163. The timer also had to have a reset switch that, when toggled, would hold the display at 00, and when toggled again, would start the timer counting up from zero again
Multisim Circuit- The first thing I did was create a circuit using the CDS MultiSim in order to get my ideas down onto paper before I put them on the PLD.
PLD Circuit- Afterwards, I uploaded the design on to the PLD (Programmable Logic Device) mode of the CDS. The circuit I created (shown below) connects a clock input to the LS163 to make the ones place increase. When a 9 is detected, 0 is loaded and the ones place starts counting from 0 again. When a 0 in the ones place is detected, the clock signals for the tens place is sent and the MSB increases by one. When a 6 is detected in the MSB, it is then instantly reset to 0.When the reset switch is set to low (off), the clear signals are set to high (on) and both displays on the counter show 0 until the reset switch is set back to high, which allows the clear signals to deactivate and therefore the clock signals are read again.
Conclusion- The difference between synchronous and asynchronous circuits is that synchronous circuits are in sync with the clock and are triggered by the rising or falling edge of the clock while asynchronous circuits are not in sync with the clock they are triggered by the values of D, J,K, Q or not Q. A '163 counter is a very unique one it starts at any number like other counters, it cannot count down, but unlike the rest the binary number you choose to stop at or use as a loop is shown instead of using the number before. A '193 is an up and down counter in that it starts at any number you want it to, but when its time to stop or loop the counter, whatever number you want to stop on you have to add one.
I am unsure exactly how my design differs from my peers, given that I wasn't entirely worried as to how they were doing. I am pretty sure, however, that I used more AND gates than was probably necessary, but I digress.
The way I approached designing of the 60 second timer, was by taking the circuit apart, and splitting it into two components: the MSI part and the SSI part of the design. My first step was to design a counter using MSI logic (which would be the one’s place) which would count up from 0-9, and then reset. The outputs of the MSI logic (which come from the 74LS93): A, B, C, and D all go through an encoder, which is then inverted, and as the outputs go through 220Ω resistors, they serve as the inputs for the Common Cathode 7-segment display, which will be wired to ground (this display will serve for the ones place in the counter). To clarify,
the snapshot of the Multisim simulation uses a Common Anode 7-segment display, which is why inverters are missing, and the display being wired up to 5V. The MSI part of the 60 second time will count to 9 and then reset to 0 because when the count reaches 10 (or 1010 in binary), that count will go through a 4-input NAND gate (output A and C will go through inverters first since they are 0’s whenever the count is 10) which will turn out combined inputs of 1, into a 0 and since input will go through a 2-input NAND gate with the SPDS switch (at high logic, or 1), the combined inputs will yield 1&0, turning into a 0 and since it is a NAND gate, it will ultimately be a 1 for the R02 input on the 74LS93. Whenever R01 (which is wired to 5V so it’s always 1) and R02 are both ones, this will make the whole MSI circuit reset to 0.
What you are going to want to do for the SSI part of the counter is first build a divided-by-two circuit using D Flip-Flops (74LS74).
You are going to want the count to go up to 6 (since this will be the display for the tens place) so the number of flip-flops used will be three. You simply find this out by taking the number of desired flip-flops and raising two to that number of flip-flops power. We have three flip-flops, so 2^3 equal 8 counts (0-7) which is exactly what you need. In this part of the process, you are tempted to want to reset the count, so that whenever the count reaches 6 it will go back to 0 (which in a way is what you want to happen) at least that is what I understood the goal to be. I had to go through a lot of trial and error in order for me to see that whenever the SPDT switch is to 0, then the whole SSI part of the 60 second counter resets to 0. You do not necessarily need a reset of 6, because you want the count to stop at 6, not reset at 6. After figuring that out, making the two separate 7-segment displays count in a decimal fashion was easy. Every time the MSI output resets to 0, you want to go up 1 in the tens place (19, 20 or 39, 40). You simply take the 4-input NAND gate output and run it through an inverter (since it will be a 0), turning it into a 1, and making the SSI design start counting.
At this point the circuit that I had was one in where all of the criteria were met, except for one: how to make the count from both MSI and SSI displays stop at 60. All you do is simply take the 110 binary output from the SSI logic (outputs C and B), which is equivalent to 6 in decimal, and run it through a 2-input NAND gate, so whenever the outputs C and B are 1’s, they will be turned into a 0. Know you take this output and connect it to a 2-input AND gate, in which the other input will be the Clock, and the output will be wired to INA on the 74LS93, making it so that whenever the count reaches 60, the counts stop, but do not reset.
I am unsure exactly how my design differs from my peers, given that I wasn't entirely worried as to how they were doing. I am pretty sure, however, that I used more AND gates than was probably necessary, but I digress.
The way I approached designing of the 60 second timer, was by taking the circuit apart, and splitting it into two components: the MSI part and the SSI part of the design. My first step was to design a counter using MSI logic (which would be the one’s place) which would count up from 0-9, and then reset. The outputs of the MSI logic (which come from the 74LS93): A, B, C, and D all go through an encoder, which is then inverted, and as the outputs go through 220Ω resistors, they serve as the inputs for the Common Cathode 7-segment display, which will be wired to ground (this display will serve for the ones place in the counter). To clarify,
the snapshot of the Multisim simulation uses a Common Anode 7-segment display, which is why inverters are missing, and the display being wired up to 5V. The MSI part of the 60 second time will count to 9 and then reset to 0 because when the count reaches 10 (or 1010 in binary), that count will go through a 4-input NAND gate (output A and C will go through inverters first since they are 0’s whenever the count is 10) which will turn out combined inputs of 1, into a 0 and since input will go through a 2-input NAND gate with the SPDS switch (at high logic, or 1), the combined inputs will yield 1&0, turning into a 0 and since it is a NAND gate, it will ultimately be a 1 for the R02 input on the 74LS93. Whenever R01 (which is wired to 5V so it’s always 1) and R02 are both ones, this will make the whole MSI circuit reset to 0.
What you are going to want to do for the SSI part of the counter is first build a divided-by-two circuit using D Flip-Flops (74LS74).
You are going to want the count to go up to 6 (since this will be the display for the tens place) so the number of flip-flops used will be three. You simply find this out by taking the number of desired flip-flops and raising two to that number of flip-flops power. We have three flip-flops, so 2^3 equal 8 counts (0-7) which is exactly what you need. In this part of the process, you are tempted to want to reset the count, so that whenever the count reaches 6 it will go back to 0 (which in a way is what you want to happen) at least that is what I understood the goal to be. I had to go through a lot of trial and error in order for me to see that whenever the SPDT switch is to 0, then the whole SSI part of the 60 second counter resets to 0. You do not necessarily need a reset of 6, because you want the count to stop at 6, not reset at 6. After figuring that out, making the two separate 7-segment displays count in a decimal fashion was easy. Every time the MSI output resets to 0, you want to go up 1 in the tens place (19, 20 or 39, 40). You simply take the 4-input NAND gate output and run it through an inverter (since it will be a 0), turning it into a 1, and making the SSI design start counting.
At this point the circuit that I had was one in where all of the criteria were met, except for one: how to make the count from both MSI and SSI displays stop at 60. All you do is simply take the 110 binary output from the SSI logic (outputs C and B), which is equivalent to 6 in decimal, and run it through a 2-input NAND gate, so whenever the outputs C and B are 1’s, they will be turned into a 0. Know you take this output and connect it to a 2-input AND gate, in which the other input will be the Clock, and the output will be wired to INA on the 74LS93, making it so that whenever the count reaches 60, the counts stop, but do not reset.